Customising RI5CY: an open-source RISC-V core

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Customising RI5CY: an open-source RISC-V core

OSHCamp 2019 Workshop – Customising RI5CY: an open-source RISC-V core

The goal of the workshop is, starting with some basic Verilog and C++ knowledge,
to design and implement some new instructions in RI5CY, a 4-stage in-order
pipelined RISC-V processor.

Workshop files

Files for the workshop are:

Slack

There is a slack for discussion following the OSHCamp workshop, for those that
wish to start or complete the workshop following OSHCamp.

It is at https://oshcampri5cyworkshop.slack.com
.

Invite link: https://join.slack.com/t/oshcampri5cyworkshop/shared_invite/enQtNzQwODQxMTgxMDYwLWM1MzUwNGU0MmQ5ODU4NmVhMjJiNTExY2QyNzU1M2RlM2QzNmZhOWMwOGVlNjg0Y2I1OTFkNDIxZGU0M2IxYmE

Basic Verilog Workshops

If you need a more basic Verilog starting point, you may wish to work through:

Other documents

There are some other useful documents included in this repository:

  • The GTKWave manual.
  • The RI5CY user manual.
  • The RISC-V ELF psABI specification.
  • The binutils RISC-V instruction formats documentation.
  • The RISC-V specification, v2.3.

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