OSHCamp 2019 Workshop – Customising RI5CY: an open-source RISC-V core
The goal of the workshop is, starting with some basic Verilog and C++ knowledge,
to design and implement some new instructions in RI5CY, a 4-stage in-order
pipelined RISC-V processor.
Files for the workshop are:
The tutorial instructions for the workshop.
Slides for the talk prior to the workshop (OSHCamp
Notes accompanying the slides.
There is a slack for discussion following the OSHCamp workshop, for those that
wish to start or complete the workshop following OSHCamp.
It is at https://oshcampri5cyworkshop.slack.com
Basic Verilog Workshops
If you need a more basic Verilog starting point, you may wish to work through:
Intro to Verilator with Verilog
uses cycle-accurate simulation.
– Using the MyStorm FPGA board.
There are some other useful documents included in this repository:
- The GTKWave manual.
- The RI5CY user manual.
- The RISC-V ELF psABI specification.
- The binutils RISC-V instruction formats documentation.
- The RISC-V specification, v2.3.