The entire computing industry has a memory problem, and a new consortium of industry partners, dubbed Gen-Z , hopes to solve it. For decades, DRAM has driven virtually every segment of the computing market, from smartphones to supercomputers, but new classes of memory devices already threaten that dominance. What’s needed is a new memory interface that can tie these various components together, and that’s where Gen-Z comes in.
Some of the problems with DRAM performance scaling are long-standing, well-known issues . Generally speaking, the amount of bandwidth available per core has continued to decrease, despite the advent of DDR4. Consider the difference between Intel’s Core i7-6950X, with 10 CPU cores and a total bandwidth of 76.8GB/s when using DDR4-2400 versus the Core i7-4960X, with six cores and 59.7GB/s of DDR3-1866. The total bandwidth available to the Core i7-6950X is higher, by nearly 30% — but the 6950X also has 10 cores and 20 threads, compared with the 4960X’s six cores and 12 threads. Total bandwidth per core has indeed gone down — from 9.95GB/s per core for the 4960X to 7.68GB/s per core for the 6950X.
This difference persists even if we assume the user steps outside Intel’s official specs and uses the highest-end RAM realistically available. A quad-channel Core i7-4960X with DDR3-3100 would offer 99.2GB/s of bandwidth (16.5GB/s of bandwidth per core) while a Core i7-6950X with DDR4-4266 offers 136.51GB/s of bandwidth, or 13.65GB/s per core. No matter which components you choose, the amount of bandwidth available per core is going down.
So instead of just beating our heads against that fundamental limit, Gen-Z wants to beef up the performance of next-generation interconnects that might be used to tap these emerging types of memory — some of which need to be connected in ways not covered by current standards.